lily 🌱<p><a href="https://mk.absturztau.be/tags/x86" rel="nofollow noopener noreferrer" target="_blank">#x86</a> <a href="https://mk.absturztau.be/tags/x87" rel="nofollow noopener noreferrer" target="_blank">#x87</a><span><br><br>i've been reading some things on bus access for the 8087-80487 series of co-processors and the way that the bus is handed in the 8087 is different from the 287 and later.<br><br>for the 8087, the co-processor has DMA and takes control of the bus when it needs to do a memory access. i note that the 8087 doesn't calculate the initial address itself - the 8086 executes a dummy read cycle when it sees a co-processor instruction and the 8087 intercepts that address to use for it's DMA.<br>this means that the CPU has zero idea how the FPU executes instructions.<br><br>on the 287 and the 387, the CPU has complete control of the bus. the CPU </span><i>tells</i><span> the FPU what kind of cycle is on the bus (is this a bus opcode cycle, a bus memory read cycle, a bus memory write cycle), and the FPU only has control over the bus's data lines which it uses when given the opportunity to write to memory.<br>the FPU is completely oblivious to the state of the bus's address lines.<br>this means that the CPU must know what kinds of instructions the FPU is executing and must partially decode the opcode in order to know what requires a memory read/write.<br><br>you can see why they decided to just put the fpu on-die for the 486.</span></p>